DocumentCode :
703829
Title :
A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems
Author :
Dev Gomony, Manil ; Garside, Jamie ; Akesson, Benny ; Audsley, Neil ; Goossens, Kees
Author_Institution :
Eindhoven Univ. of Technol., Eindhoven, Netherlands
fYear :
2015
fDate :
9-13 March 2015
Firstpage :
193
Lastpage :
198
Abstract :
Predictable arbitration policies, such as Time Division Multiplexing (TDM) and Round-Robin (RR), are used to provide firm real-time guarantees to clients sharing a single memory resource (DRAM) between the multiple memory clients in multi-core real-time systems. Traditional centralized implementations of predictable arbitration policies in a shared memory bus or interconnect are not scalable in terms of the number of clients. On the other hand, existing distributed memory interconnects are either globally arbitrated, which do not offer diverse service according to the heterogeneous client requirements, or locally arbitrated, which suffers from larger area, power and latency overhead. Moreover, selecting the right arbitration policy according to the diverse and dynamic client requirements in reusable platforms requires a generic re-configurable architecture supporting different arbitration policies. The main contributions in this paper are: (1) We propose a novel generic, scalable and globally arbitrated memory tree (GSMT) architecture for distributed implementation of several predictable arbitration policies. (2) We present an RTL-level implementation of Accounting and Priority assignment (APA) logic of GSMT that can be configured with five different arbitration policies typically used for shared memory access in real-time systems. (3) We compare the performance of GSMT with different centralized implementations by synthesizing the designs in a 40 nm process. Our experiments show that with 64 clients GSMT can run up to four times faster than traditional architectures and have over 51% and 37% reduction in area and power consumption, respectively.
Keywords :
DRAM chips; multiprocessing systems; real-time systems; time division multiplexing; APA logic; GSMT architecture; RR; TDM; accounting and priority assignment; distributed memory interconnects; diverse client requirements; dynamic client requirements; generic arbitrated memory tree; globally arbitrated memory tree; multicore real-time systems; real-time systems; round-robin; scalable arbitrated memory tree; shared DRAM access; shared memory bus; single memory resource; time division multiplexing; Bandwidth; Clocks; Real-time systems; Registers; Silicon; Time division multiplexing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location :
Grenoble
Print_ISBN :
978-3-9815-3704-8
Type :
conf
Filename :
7092381
Link To Document :
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