A packet-switched interconnect for many-core systems with BE and RT service

A packet-switched interconnect design which supports real-time and best-effort services is proposed. This interconnect is different from traditional NoCs in that we use direction channels to replace the large input buffers and use less resource to realize the network transfer. The connection between our interconnect design and IP core is an on-chip memory management block named DME. The real-time service implies preferential transfer channel allocation, maximum delay bound and time stamping of every real-time packet. The solution is geared towards many-core systems, such as complex industrial control systems and communication devices, which require these features to facilitate efficient SW and application development.