• DocumentCode
    704017
  • Title

    Monolithic 3D integration: A path from concept to reality

  • Author

    Shulaker, Max M. ; Wu, Tony F. ; Sabry, Mohamed M. ; Hai Wei ; Wong, H.-S Philip ; Mitra, Subhasish

  • fYear
    2015
  • fDate
    9-13 March 2015
  • Firstpage
    1197
  • Lastpage
    1202
  • Abstract
    Monolithic three-dimensional (3D) integration enables revolutionary digital system architectures of computation immersed in memory. Vertically-stacked layers of logic circuits and memories, with nano-scale inter-layer vias (with the same pitch and dimensions as tight-pitched metal layer vias), provide massive connectivity between the layers. The nano-scale inter-layer vias are orders of magnitude denser than conventional through silicon vias (TSVs). Such digital system architectures can achieve significant performance and energy efficiency benefits compared to today´s designs. The massive vertical connectivity makes such architectures particularly attractive for abundant-data applications that impose stringent requirements with respect to low-latency data processing, high-bandwidth data transfer, and energy-efficient storage of massive amounts of data. We present an overview of our progress toward realizing monolithic 3D ICs, enabled by recent advances in emerging nanotechnologies such as carbon nanotube field-effect transistors and emerging memory technologies such as Resistive RAMs and Spin-Transfer Torque RAMs.
  • Keywords
    energy conservation; logic circuits; monolithic integrated circuits; nanotechnology; three-dimensional integrated circuits; TSV; abundant-data applications; carbon nanotube field-effect transistors; energy-efficient storage; high-bandwidth data transfer; logic circuits; logic memory; low-latency data processing; magnitude denser; massive vertical connectivity; monolithic 3D IC integration; monolithic three-dimensional integration; nanoscale interlayer vias; nanotechnology; resistive RAM; revolutionary digital system architectures; spin-transfer torque RAM; stringent requirements; through-silicon-vias; tight-pitched metal layer vias; vertically-stacked layers; CMOS integrated circuits; CNTFETs; Energy efficiency; Logic gates; Silicon; Three-dimensional displays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
  • Conference_Location
    Grenoble
  • Print_ISBN
    978-3-9815-3704-8
  • Type

    conf

  • Filename
    7092569