Title :
An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip
Author :
Salamat, Ronak ; Ebrahimi, Masoumeh ; Bagherzadeh, Nader
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Irvine, Irvine, CA, USA
Abstract :
The cost and reliability issues of TSVs move 3D-NoCs toward heterogonous designs with limited number of TSVs. However, designing a deadlock-free routing algorithm for such heterogonous architectures is extremely challenging due to the increased possibilities of forming cycles between and within layers for 3D designs. In this paper, we target designing a routing algorithm for heterogeneous 3D-NoCs with the capability of working under the technical limit in which there is just one TSV in the network. This algorithm is light-weight and provides adaptivity by using only one virtual channel along the Y dimension.
Keywords :
fault tolerant computing; integrated circuit design; integrated circuit reliability; network-on-chip; three-dimensional integrated circuits; TSV technology; adaptive routing algorithm; deadlock-free routing algorithm; fault resilient routing algorithm; heterogonous 3D network-on-chip; heterogonous architectures; heterogonous designs; low restrictive routing algorithm; through-silicon-via technology; virtual channel; Algorithm design and analysis; Elevators; Fault tolerance; Routing; System recovery; Three-dimensional displays; Through-silicon vias;
Conference_Titel :
Parallel, Distributed and Network-Based Processing (PDP), 2015 23rd Euromicro International Conference on
Conference_Location :
Turku
DOI :
10.1109/PDP.2015.91
