• DocumentCode
    704356
  • Title

    Passivity Verification and Macromodel Interpolation Using Singular Value Decomposition (SVD)

  • Author

    Elgamel, Dalia ; Greeff, Roy ; Ovard, David

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Idaho, Moscow, ID, USA
  • fYear
    2015
  • fDate
    20-20 March 2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Approximation of the Rational Function (RF) order plays a key role in passivity checking of large interconnect memory design. RF approximation can be estimated using the Least- square solutions; the Singular Value Decomposition (SVD) is used to solve large order macromodels. The interpolation method is used to solve linear systems by approximating the RF degree and coefficients. However, building the macromodel requires RF order approximation, which can lead to inaccurate passivity checking for complex systems. While inaccurate order estimation may lead to inaccuracy in the passivity checking process and drive to unnecessary passivity enforcement to the macromodel. Inaccurate passivity enforcement perturbation may cause large error adds up to the RF approximation, and may change the original design characteristics. Thus, passivity verification for larger order models requires determining the RF order, using the SVD resolved the inaccurate prior estimation of the model order, yet it yields to an exact solution. SVD is considered an expensive computational algorithm, but SVD shows accurate models order approximation. Using the SVD solved the problem associated with the passivity checking algorithm, which is estimating the initial number of poles or the model order. However, the correlation between determining the model order degree and passivity checking did not exist before. The DC frequency band and the truncation frequency point may lead to some residuals that affect the accuracy of this estimation. Using SVD to solve linear systems enhances the passivity checking of DRAM memory package and high end computers reduces the computation time.
  • Keywords
    DRAM chips; integrated circuit modelling; interpolation; rational functions; singular value decomposition; DRAM memory package; macromodel interpolation; passivity verification; rational function; singular value decomposition; Approximation methods; Computational modeling; Linear systems; Mathematical model; Numerical models; Radio frequency; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics and Electron Devices (WMED), 2015 IEEE Workshop on
  • Conference_Location
    Boise, ID
  • ISSN
    1947-3834
  • Print_ISBN
    978-1-4799-7644-7
  • Type

    conf

  • DOI
    10.1109/WMED.2015.7093692
  • Filename
    7093692