Title :
A novel hardware-friendly self-adjustable offset min-sum algorithm for ISDB-S2 LDPC decoder
Author :
Wen Ji ; Hamaminato, Makoto ; Nakayama, Hiroshi ; Goto, Satoshi
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
In this paper, a novel self-adjustable offset min-sum LDPC decoding algorithm is proposed for ISDB-S2 (Integrated Services Digital Broadcasting via Satellite - Second Generation) application. We present for the first time a uniform approximation of the check node operation through mathematical induction on Jacobian logarithm. The approximation theoretically shows that the offset value is mainly dependent on the difference between the two most unreliable inputs from the bit nodes and the algorithm proposed can adjust the offset value according to the inputs during the iterative decoding procedure. Simulation results for all 11 code rates of ISDB-S2 demonstrate that the proposed method can achieve an average of 0.15dB gain under the same Bit Error Rate (BER) performance, compared to the Min-sum based algorithms, and consumes only 1.21% computation complexity compared to BP-based algorithms in the best case.
Keywords :
ISDN; approximation theory; computational complexity; direct broadcasting by satellite; error statistics; iterative decoding; parity check codes; BER; ISDB-S2 LDPC decoder; Jacobian logarithm; approximation theory; bit error rate; computation complexity; hardware-friendly self-adjustable offset min-sum algorithm; integrated service digital broadcasting via satellite-second generation application; iterative decoding; Approximation algorithms; Communication standards; Data communication; Digital multimedia broadcasting; Hardware; Manganese; Mathematical model;
Conference_Titel :
Signal Processing Conference, 2010 18th European
Conference_Location :
Aalborg