Rapid prototyping of image analysis algorithms on an adaptive FGPA architecture

The aim of this work is to propose a fast and reliable design flow for the implementation of some image analysis algorithms on an adaptive architecture using an FPGA platform. This adaptive architecture is designed in a Globally Asynchronous Locally Synchronous (GALS) approach so that the hardware resources are stand-alone modules. Any modification only affects the target module, not the entire system. The design flow associated to this architecture includes IP libraries for all reused modules and a high-level development tool called Handle-C for the design of new modules. The image processing designer implements any image analysis algorithm in a reliable way without any hardware specialist.