Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system

The design of complex Digital Signal Processing (DSP) hardware accelerators implies to minimize architectural cost and to maximize timing performances. Exploring different communication architectures and timing behaviors is thus a key step in the modern system design flows. In this paper, we present a methodology that permits the design space exploration of DSP applications. The proposed approach consists in embedding a sequential function into a Behavioral Description Model (BDM) that includes a set of I/O and control processes. Communication architectures and timing behaviors (I/O scheduling, I/O parallelism...) can be varied and easily explored by adding I/O and synchronization code into the dedicated concurrent processes while keeping the functionality description unchanged throughout the exploration step. A high-level synthesis tool is next used to generate the architectures that respect the design constraints. We show the interest of our approach in the case study of a Hyper-plane Intersection and Selection HIS algorithm for MC-CDMA system.