High-level synthesis heuristics for run-time reconfigurable architectures

High-level synthesis is becoming more popular as design densities keep increasing in both the ASIC and FPGA world. Additionally, modern programmable devices offer the advantage of partial reconfiguration, which allows an algorithm to be partially mapped into a small and fixed FPGA device that can be reconfigured at run time, as the mapped application changes its requirements. This paper presents resource constrained high-level synthesis heuristics, which utilize reconfigurable datapath components under a variety of implementation platforms. The resulting architectures can be shortened so that the gain in clock cycles outperforms the timing overhead of reconfiguration. The main advantage of the proposed methodology is that through run time reconfiguration, more complicated algorithms can be mapped into smaller devices without speed degradation.