DocumentCode
706158
Title
A lossless compression system realization utilizing phit-serial network-on-chip paradigm
Author
Dziurzanski, P. ; Maka, T. ; Ulacha, G. ; Stasinski, R.
Author_Institution
Fac. of Comput. Sci. & Inf. Syst., Szczecin Univ. of Technol., Szczecin, Poland
fYear
2007
fDate
3-7 Sept. 2007
Firstpage
1691
Lastpage
1695
Abstract
The routing efficiency of on-chip networks remains an open problem for system engineers dealing with multi-core processors. The presented research includes consideration of phit-serial links in a Network-on-Chip (NoC) architecture. We propose measures for communication overhead for a single wormhole router embedded in a square mesh plane. As a source of data bit-stream, we use a lossless compression system based on blending predictors. According to the experimental results, the influence of flow control unit (flit) and physical control digit (phit) lengths on total transfer time is of a non-linear character. The transfer time is proportional to the flit length and inverse proportional to the phit size.
Keywords
integrated circuit design; microprocessor chips; multiprocessing systems; network-on-chip; flow control unit; lossless compression system realization; multi-core processors; network-on-chip architecture; on-chip networks; phit-serial links; phit-serial network-on-chip paradigm; physical control digit; routing efficiency; system engineers; Clocks; Europe; IP networks; Routing; Synchronization; System-on-chip; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Conference, 2007 15th European
Conference_Location
Poznan
Print_ISBN
978-839-2134-04-6
Type
conf
Filename
7099095
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