FPGA implementation of dual key based AES encryption with key Based S-Box generation

Network security is an emerging domain of communication. Cryptography plays an important role in providing a secure network for communication. The most secure block cipher today is Rijndael cipher also known as AES. But with advanced research happening in the field of cryptography, the conventional scheme of AES is vulnerable for cryptanalysis. Hence a lot of changes have been proposed on this algorithm. Static S-Boxes are implemented using look up tables which will never vary with the input text or input key. This consumes a lot of Memory for the storage of look up table. Also this technique makes reverse engineering very simple for the purpose of cryptanalysis. Thus it is essential to generate S-Bytes at run time. It is beneficial if the S-byte generated during run time varies with the input key. Another weakness of AES is that it works with a single key. The confidentiality of the key determines the security of the algorithm. In this paper, a new scheme of AES involving generation of Key based S-Boxes and dual key AES is proposed. This overcomes the vulnerability of static S-Boxes and also single key encryption scheme. In this paper, the architecture of the algorithm for optimal FPGA implementation is also proposed.