Resistive Computation: A Critique

Author

Mahmoodi, Hamid ; Lakshmipuram, Sridevi Srinivasan ; Arora, Manish ; Asgarieh, Yashar ; Homayoun, Houman ; Lin, Bo ; Tullsen, Dean M.

Author_Institution

Univ. of California, San Diego, La Jolla, CA, USA

Volume

13

Issue

2

fYear

2014

fDate

July-Dec. 4 2014

Firstpage

89

Lastpage

92

Abstract

Resistive Computation was suggested by [6] as an idea for tacking the power wall by replacing conventional CMOS logic with Magnetic Tunnel Junction (MTJ) based Look-Up Tables (LUTs). Spin Transfer Torque RAM (STTRAM) is an emerging CMOS-compatible non-volatile memory technology based on Magnetic Tunnel Junctions as a memory bit [3]. The principal advantage of STTRAM is that it is leakage-resistant, which is an important characteristic beyond the 45nm technology node, where leakage concerns are becoming a limiting factor in microprocessor performance. Although STTRAM is a good candidate for replacing SRAM for on-chip memory, we argue in this article MTJ-based LUTs are unnecessarily expensive in terms of area, power, and performance when implementing fixed combinational logic that does not require the reprogramming ability provided by MTJs.

Keywords

magnetic tunnelling; random-access storage; table lookup; CMOS-compatible nonvolatile memory technology; MTJ-based LUT; STTRAM; fixed combinational logic; leakage-resistance; look-up tables; magnetic tunnel junction; memory bit; resistive computation; spin transfer torque RAM; CMOS integrated circuits; Delays; Logic gates; Low power electronics; Magnetic tunneling; Power distribution; Table lookup; Transistors; B.2.1 Design Styles; B.6.1.e Memory used as logic; B.7.1.a Advanced technologies; B.9.1 Low-power design; C.0.a Emerging technologies; MRAM; Resistive computation; dynamic current-mode logic; leakage power; magnetic-tunnel junctions; spin transfer torque RAM;

fLanguage

English

Journal_Title

Computer Architecture Letters

Publisher

ieee

ISSN

1556-6056

Type

jour

DOI

10.1109/L-CA.2013.23

Filename

6574859