An optimized layout with low parasitic inductances for GaN HEMTs based DC-DC converter

Reducing parasitic inductances are critical for improving efficiency and safety in Gallium Nitride (GaN) based DC-DC Converter. This paper aims at reducing the driver loop inductance and power loop inductance by optimizing the PCB layout. Firstly, this paper compares three different kinds of driver loop layouts by Maxwell 3D simulation. The results show that the driver loop inductances of single-layer layout with a shielding layer and double-layers layout are much smaller than that of the conventional single-layer layout. Then a novel doublesided layout is proposed, which has a small power loop inductance because the magnetic field is significantly canceled by the interleaved current. Finally, the design is verified by a buck converter operating at an input voltage of 12 V, an output voltage of 3.3 V, and an output current of 8 A. Experimental results show that the power loop inductance is about 0.1nH, which reduces 75% than that of the reported best layout.