DocumentCode
708640
Title
Compact modeling and parameter extraction strategy of normally-on MOSFET
Author
Umeda, T. ; Hirano, Y. ; Suzuki, D. ; Tone, A. ; Inoue, T. ; Kikuchihara, H. ; Miura-Mattausch, M. ; Mattausch, H.J.
Author_Institution
Grad. Sch. of Adv. Sci. of Matter, Hiroshima Univ., Higashi-Hiroshima, Japan
fYear
2015
fDate
23-26 March 2015
Firstpage
29
Lastpage
32
Abstract
The additional channel-dopant layer of normally-on MOSFETs leads to accumulation-layer current near channel surface and deeper-lying neutral-region current above the p/n junction, which dominate bias conditions above and below flat-band, respectively. The developed compact model accurately captures these currents and exploits their different bias-condition properties for efficient parameter extraction.
Keywords
MOSFET; accumulation layers; p-n junctions; semiconductor device models; accumulation-layer current; bias condition properties; channel surface; channel-dopant layer; compact modeling; deeper-lying neutral-region current; normally-on MOSFET; p-n junction; parameter extraction strategy; Electric potential; Lead; MOSFET; MOSFET circuits; Mathematical model; Semiconductor device modeling; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures (ICMTS), 2015 International Conference on
Conference_Location
Tempe, AZ
ISSN
1071-9032
Print_ISBN
978-1-4799-8302-5
Type
conf
DOI
10.1109/ICMTS.2015.7106103
Filename
7106103
Link To Document