A four-terminal JFET compact model for high-voltage power applications

This paper presents a physics-based compact model for four-terminal (4T) JFETs. It is capable of modeling device characteristics when the top and bottom gates are biased independently. The model is formulated using symmetric linearization technique from the CMC (compact model council) standard MOSFET model PSP, which gives simpler model equations than other reported 4T JFET models. It also includes carrier velocity saturation effect which is important for short channel and/or high voltage devices. The model has been verified on several JFETs (including device with blocking voltage rated > 700V). Good agreement has been achieved between silicon data and simulation. The complete model has been implemented into process design kits (PDKs) for high-voltage power management switcher design.