Accelerating 14nm device learning and yield ramp using parallel test structures as part of a new inline parametric test strategy

Author

Moore, Garry ; Jiun-Hsin Liao ; McDade, Scott ; Verzi, Bill

Author_Institution

IBM Microelectron., Hopewell Junction, VA, USA

fYear

2015

fDate

23-26 March 2015

Firstpage

44

Lastpage

49

Abstract

This paper will look at both technical and business advantages of parallel vs. serial inline parametric testing, secondary effects of changing test strategies, quantifying return on investment of newer test strategies, and next steps in pushing the envelope of test. Topics such as cost, schedule, macro design and quality will be explored to understand tradeoffs and synergies of test strategies. Examples and metrics of parallel compared to serial testing will be examined.

Keywords

field effect transistors; semiconductor device testing; changing test strategy; complex parallel FET testing; cost; device learning; macro design; parallel inline parametric test strategy; parallel test structures; quality; schedule; secondary effects; serial inline parametric testing strategy; size 14 nm; yield ramp; Capacitance; Electronic mail; Investment; Layout; Probes; Testing; Throughput; In-line test; parallel test; parameter per hour; parametric test;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures (ICMTS), 2015 International Conference on

Conference_Location

Tempe, AZ

ISSN

1071-9032

Print_ISBN

978-1-4799-8302-5

Type

conf

DOI

10.1109/ICMTS.2015.7106106

Filename

7106106