Compact modeling solution of layout dependent effect for FinFET technology

Author

Chen, David C. ; Guan Shyan Lin ; Tien Hua Lee ; Lee, Ryan ; Liu, Y.C. ; Meng Fan Wang ; Yi Ching Cheng ; Wu, D.Y.

Author_Institution

Adv. Technol. Dev. Div., United Microelectron. Corp. (UMC), Hsinchu, Taiwan

fYear

2015

fDate

23-26 March 2015

Firstpage

110

Lastpage

115

Abstract

We successfully developed and verified a complete compact model solution for layout dependent effect (LDE) of FinFET technology. LDE has significant impact on the device performances mainly due to the application of stressors and aggressive device scaling. With LDE, performance degradation may be up to 10% or more. In this work, compact model solution for Length of Oxidation (LOD), Well Proximity Effect (WPE), Neighboring Diffusion Effect (NDE), Metal Boundary Effect (MBE), and Gate Line End Effect (GLE) were delivered. This solution was implemented successfully in BSIM-CMG for efficient circuit simulation.

Keywords

MOSFET; diffusion; oxidation; proximity effect (lithography); semiconductor device models; semiconductor-metal boundaries; BSIM-CMG; FinFET technology; aggressive device scaling; compact modeling solution; gate line end effect; layout dependent effect; length of oxidation; metal boundary effect; neighboring diffusion effect; performance degradation; stressors; well proximity effect; FinFETs; Layout; Logic gates; MOSFET circuits; Mathematical model; Metals; Performance evaluation;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures (ICMTS), 2015 International Conference on

Conference_Location

Tempe, AZ

ISSN

1071-9032

Print_ISBN

978-1-4799-8302-5

Type

conf

DOI

10.1109/ICMTS.2015.7106119

Filename

7106119