DocumentCode
708666
Title
Test circuit for accurate measurement of setup/hold and access time of memories
Author
Agarwal, Neha
Author_Institution
Phys. Design Group, ARM Embedded Technol. Pvt. Ltd., Bangalore, India
fYear
2015
fDate
23-26 March 2015
Firstpage
204
Lastpage
206
Abstract
This paper will examine the latest developments in the field of designing the test circuits for accurate measurement of setup/hold and access time of memory IPs. Measurement across all voltage domain and temperature corners, by way of the architecture discussed, has a fine resolution of just two inverter delay and correlates well with silicon within permissible range.
Keywords
circuit testing; temperature measurement; time measurement; voltage measurement; access time measurement; circuit testing; inverter delay; memory IP; setup-hold time measurement; temperature measurement; voltage measurement; DH-HEMTs; Delays; Flip-flops; Integrated circuit interconnections; Inverters; Libraries; Semiconductor device measurement; access; hold; memory; setup; test chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures (ICMTS), 2015 International Conference on
Conference_Location
Tempe, AZ
ISSN
1071-9032
Print_ISBN
978-1-4799-8302-5
Type
conf
DOI
10.1109/ICMTS.2015.7106153
Filename
7106153
Link To Document