Reducing power-supply and ground noise induced timing jitter in short pulse generation circuits

Author

Jiwei Sun ; Pingshan Wang ; Hanqiao Zhang

Author_Institution

Dept. of Electr. & Comput. Eng., Clemson Univ., Clemson, SC, USA

fYear

2015

fDate

15-21 March 2015

Firstpage

17

Lastpage

21

Abstract

This paper presents a study of power-supply noise and ground noise impact on the timing properties of short pulse generation circuits. The timing jitter of the measured pulses is mainly from the trigger pulse generator in the circuit consisting of conventional CMOS inverters and NAND gates. Furthermore, the response surface model combined with Latin Hypercube Sampling (LHS) is proposed to model the timing jitter of short pulse generation circuits. The analytical model is verified with Cadence using 0.13 μm CMOS technology. In order to reduce the timing jitter, MOS current-mode logic (MCML) circuits are used in the trigger pulse generator. Up to 50% improvement on the timing jitter can be obtained, due to the differential structure of MCML circuits.

Keywords

CMOS logic circuits; current-mode logic; integrated circuit modelling; logic gates; pulse generators; response surface methodology; timing jitter; trigger circuits; CMOS technology; Cadence; MCML circuits; MOS current-mode logic circuits; ground noise-induced timing jitter reduction; power-supply noise-induced timing jitter reduction; short-pulse generation circuits; timing properties; trigger pulse generator; CMOS integrated circuits; Integrated circuit modeling; Inverters; Logic gates; Noise; Pulse generation; Timing jitter; Inverter; MCML; NAND; ground noise; latin hypercube sampling; power-supply noise; response surface model; short pulse generation circuit; timing jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility and Signal Integrity, 2015 IEEE Symposium on

Conference_Location

Santa Clara, CA

Print_ISBN

978-1-4799-1992-5

Type

conf

DOI

10.1109/EMCSI.2015.7107652

Filename

7107652