Enhanced gain bandwidth and loss compensated cascaded single-stage CMOS distributed amplifier

This work presents a loss compensated cascaded single-stage distributed amplifier (CSSDA) in commercial 65nm CMOS technology. The CSSDA is composed of three distributed stages connected in a cascade configuration to target high gain. The idle interstage drain terminations are omitted because of multiplicative gain mechanism. High gain is maintained over very large bandwidth through the inductive-peaking technique. Further, the CSSDA single cell is modified by a loss compensation technique to remove the high frequency losses of the artificial transmission lines which shows a significant enhancement in gain bandwidth (GBW) product. The simulation results show a GBW of 540GHz for the loss compensated CSSDA (LC-CSSDA) which is significantly higher than GBW of 350 GHz for a conventional CSSDA. The 2-stage (LC-CSSDA) shows a GBW of 835GHz which is almost twice the GBW (426 GHz) of a conventional 2-stage CSSDA.