• DocumentCode
    709665
  • Title

    Warpage modeling technique of organic interposer considering deformation by insulator material shrinkage

  • Author

    Okamoto, Keishi ; Kohara, Sayuri ; Noma, Hirokazu ; Toriyama, Kazushige ; Mori, Hiroyuki

  • Author_Institution
    Electron. & Opt. Packaging, IBM Res. - Tokyo, Kawasaki, Japan
  • fYear
    2015
  • fDate
    14-17 April 2015
  • Firstpage
    771
  • Lastpage
    775
  • Abstract
    The increase of organic interposer warpage in large-die fine-pitch flip-chip package applications makes more challenging for C4 bumps on chip to be connected to solder on the interposer pads during reflow process for chip attach. Therefore the pattern layout and material selection of the interposer should be optimized to minimize the warpage during the reflow. In order to do that, it is essential to establish a precise mechanical modeling methodology to predict warpage behavior in earlier stage of design. In the typical modeling, initial warpage at final lamination process of interposer manufacturing is assumed to be zero. However the actual has some deformation caused by such as resin cure shrinkage and handling at manufacturing operations. It can´t be ignored on the prediction and results in the accuracy limitation. In this paper, we focus on the warpage behavior of organic laminates consisting of glass reinforced core, build-up and solder resist materials which have been widely used for application processor of mobile applications and high-end microprocessors. Firstly, we try to characterize the cure shrinkage of build-up and solder resist materials. Then we try to make a new modeling technique for the warpage prediction simulating the actual laminate manufacturing process steps considering such material shrinkage. The results of the warpage by the new models are indicating that the technique can realize the shape of the initial warpage just after laminate manufacturing line.
  • Keywords
    flip-chip devices; resins; solders; C4 bumps; application processor; chip attach; deformation; glass reinforced core; high-end microprocessors; insulator material shrinkage; interposer manufacturing; interposer pads; laminate manufacturing line; large-die fine-pitch flip-chip package applications; manufacturing operations; material selection; material shrinkage; mechanical modeling methodology; mobile applications; organic interposer; organic laminates; pattern layout; reflow process; resin cure shrinkage; solder resist materials; warpage modeling technique; Finite element analysis; Laminates; Manufacturing processes; Semiconductor device measurement; Semiconductor device modeling; Shape; Temperature measurement; Finite Element Method; Organic intereposer; Warpage; insulator material shrinkage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging and iMAPS All Asia Conference (ICEP-IACC), 2015 International Conference on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-4-9040-9012-1
  • Type

    conf

  • DOI
    10.1109/ICEP-IAAC.2015.7111114
  • Filename
    7111114