Optimum configuration of SI/PI Co-Simulation using electro-magnetic simulator

Signal Integrity (SI) of single-ended digital communication devices, like DDR memory, is directly vulnerable to Power Integrity (PI) issues because the current return path flows from power to ground through the signal lines. Accurate simulation of the interaction between both signal lines and the Power Delivery Network (PDN) is essential for estimating system reliability before fabricating the printed circuit board (PCB). To achieve this goal, electro-magnetic (EM) simulation is commonly used rather than measurement by a vector network analyzer. This simulation approach is possible, but modeling the full PDN with critical signal lines on a large PCB can absorb prohibitive long simulation time given the ever faster design cycles of modern electronics. This paper provides the pros and cons of optimizing the PDN size relative to the signal lines to reduce SI/PI Co-Simulation time for EM solvers. The results of the simulations is validated by measurement and the ideas are extended to more realistic case with deductive approach.