SRAM stability design comprehending 14nm FinFET reliability

Importance of low voltage operation of SRAM in mobile application is ever increasing for longer battery life. SRAM occupies a significant portion of the total area and power for the SOC ICs (>10-30MByte used in AP/CPUs). For the operation of SRAM at low voltage, proper noise margin for read, disturb and write operation is important since noise margin reduces with technology scaling and low voltage operation. Previously, we presented a method on SRAM Vmin design and characterization before and after High Temperature Operating Life (HTOL) stress test [1-3]. In this work, we extend our method to account for end-of-life aging into statistical SRAM cell design with Z-score method on 14nm FinFET technology. Excellent Vmin behavior at both time0 and EOL satisfying 10yrs was demonstrated at the product level.