DocumentCode
710357
Title
Clock-domain-aware test for improving pattern compression
Author
Kun-Han Tsai ; Rajski, Janusz
Author_Institution
Mentor Graphics Corp., Wilsonville, OR, USA
fYear
2015
fDate
27-29 April 2015
Firstpage
1
Lastpage
4
Abstract
This paper proposes an integration method between DFT and ATPG to improve the pattern compression by pulsing interactive clocks (PIC) simultaneously. The proposed algorithm can accurately mask the unreliable cross clock domain transitions for any clock skews. In addition, it identifies the required flops to be inserted hold paths, and combined with ATPG to reduce the pattern count by up to 39% without compromising the test quality.
Keywords
integrated circuit design; integrated circuit testing; ATPG; DFT; IC design; PIC; clock skews; clock-domain-aware test; cross clock domain transitions; integration method; pattern compression improvement; pulsing interactive clocks; Automatic test pattern generation; Clocks; Discrete Fourier transforms; Hardware; Logic gates; Silicon; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on
Conference_Location
Hsinchu
Type
conf
DOI
10.1109/VLSI-DAT.2015.7114506
Filename
7114506
Link To Document