SoC test integration platform

Most of the ASIC designs that we currently encountered are SoC in nature. The success of SoC design methodology relies on the design reuse of existing cores (IPs). The tasks of integrating the cores and creating successful tests for the SoC should not be overlooked. These tasks may need a considerable amount of time from the designers and are inherently error-prone. Conventionally, designers have to understand the test requirement of all the IPs used in the SoC. A test plan is then created and the corresponding test wrapper for the IPs is added and integrated into the SoC design. Besides IPs test integration, designers typically need to plan for the scan DfT, test compression, test wrapper, memory BIST, and boundary scan. The above tasks are pretty standard, yet they are tedious and error-prone.