A 25Gbps 3D-integrated CMOS/silicon photonic optical receiver with −15dBm sensitivity and 0.17pJ/bit energy efficiency

Summary form only given. Recent advances in silicon photonic devices and 3D integration have enabled them to be a viable solution for dense chip-to-chip interconnection. A key design metric for interconnects is the link power efficiency at a specific distance. In a modulator-based optical link, power is dissipated not only in the electronic circuitry, but also in the laser source. Improving the sensitivity of the receiver, which translates to lower laser power, can significantly reduce the power consumption of the link. In this work, a highly sensitive receiver topology is presented that is suitable for ultra-low capacitance front-ends. Low capacitance has become feasible by 3D integration of CMOS chip with a silicon-photonic (SiPh) chip containing a waveguide-coupled photodiode. The 3D integration is based on Copper Pillar (CuP) flip-chip bonding that enables low parasitic capacitance and dense interconnections with the SiPh (40μm pitch). For comparison purposes two CMOS receivers are integrated with the same SiPh chip. Both prototypes are fabricated in a 28nm CMOS technology.