Enhancement-mode GaN-on-Si MOS-FET using Au-free Si process and its operation in PFC system with high-efficiency

Author

Miyamoto, Hironobu ; Okamoto, Yasuhiro ; Kawaguchi, Hiroshi ; Miura, Yoshinao ; Nakamura, Makoto ; Nakayama, Tatsuo ; Masumoto, Ichiro ; Miyake, Shinichi ; Hirai, Tomohiro ; Fujita, Machiko ; Ueda, Takehiro ; Yamanoguchi, Katsumi ; Tsuboi, Atsushi

Author_Institution

Technol. Div., Renesas Semicond. Manuf. Co., Ltd., Otsu, Japan

fYear

2015

fDate

10-14 May 2015

Firstpage

209

Lastpage

212

Abstract

We have developed an enhancement-mode GaN-on-Si MOS-FET with a thin GaN channel (40nm) on a thick AlGaN back barrier layer (1um), using Au-free 150-mm Si process. The developed device showed a threshold voltage Vt of 1.1 V, an on-resistance Ron of 5.4 mΩcm2 and a breakdown voltage BV of 730 V. The developed E-mode GaN MOS-FETs demonstrated the potential for compact and efficient power electronics. A Power Factor Correction (PFC) circuit using the packaged GaN device (20A, 650V) operated with high efficiency of > 94 % at Pout=300 W, Vout=390 V and f_SW=300 kHz.

Keywords

III-V semiconductors; elemental semiconductors; gold compounds; power MOSFET; power factor correction; silicon compounds; PFC circuit; breakdown voltage; current 20 A; enhancement-mode gallium nitride-on-silicon MOS-FET; gold-free 150-mm silicon process; power 300 W; power electronics; power factor correction circuit; thin gallium nitride channel; threshold voltage; voltage 1.1 V; voltage 390 V; voltage 650 V; Aluminum gallium nitride; Aluminum oxide; Gallium nitride; Logic gates; Silicon; Threshold voltage; Wide band gap semiconductors; GaN; MOSFET; PFC circuit; enhancement-mode;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices & IC's (ISPSD), 2015 IEEE 27th International Symposium on

Conference_Location

Hong Kong

ISSN

1943-653X

Print_ISBN

978-1-4799-6259-4

Type

conf

DOI

10.1109/ISPSD.2015.7123426

Filename

7123426