Analysis of low power methods in 14T full adder

Apart from static power loss, leakage power loss is considerably increasing with scaling. This paper analyses techniques for power reduction to be integrated to the 14T full adder circuit to achieve low power reliable full adder circuits. However, to perform an arithmetic operation, a device can use up very low power by functioning at very low frequency but it may spend a very long time to finish the operation. Therefore, we measure the power dissipation and evaluate the performance of the system by calculating the Power-Delay Product (PDP), which is the product of average power consumption and delay. Power delay product at various supply voltages for different feature sizes has been considered for reliable results.