Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits

Author

Cheoljon Jang ; Jaehwan Kim ; Byunggyu Ahn ; Jongwha Chong

Author_Institution

Dept. of Electron. Comput. Eng., Hanyang Univ., Seoul, South Korea

Volume

7

Issue

1

fYear

2013

fDate

Jan. 2013

Firstpage

11

Lastpage

20

Abstract

Three-dimensional-integrated circuits (3D-ICs) bring new issues for power delivery network design because of larger current density and more complicated power delivery paths compared to 2D-IC. The power delivery network consists of power bumps, through-silicon-vias (TSVs), and power wires. IR-drop at each node varies with the number and position of power bumps and TSVs. These three power resources affect IR-drop of 3D-ICs. In this study, the authors propose power delivery network design methodology to optimise power resources wherease IR-drop constraint is satisfied. The simulation results show that the proposed method minimises the number of power bumps and TSVs compared to the conventional method.

Keywords

integrated circuit design; three-dimensional integrated circuits; 2D-IC; 3D-IC; IR-drop constraint; TSV; current density; power bumps; power delivery network design methodology; power delivery paths; power mesh structure optimisation; power resources optimisation; power wires; three-dimensional-integrated circuits; through-silicon-vias placement;

fLanguage

English

Journal_Title

Computers & Digital Techniques, IET

Publisher

iet

ISSN

1751-8601

Type

jour

DOI

10.1049/iet-cdt.2012.0047

Filename

6518043