DocumentCode
715912
Title
An ECC-based memory architecture with online self-repair capabilities for reliability enhancement
Author
Gian Mayuga ; Yamato, Yuta ; Yoneda, Tomokazu ; Inoue, Michiko ; Sato, Yasuo
Author_Institution
Nara Inst. of Sci. & Technol., Nara, Japan
fYear
2015
fDate
25-29 May 2015
Firstpage
1
Lastpage
6
Abstract
Embedded memory is extensively being used in SoCs, and is rapidly growing in size and density. To keep up with the development pace of nanoscale devices, enhancement methods for yield and reliability must overcome the barriers set forth by advent of new technology. To address the issue of reliability, periodic online field test and repair are implemented by using synergistic approach of employing redundancy and ECC to repair or correct both hard errors and soft errors. In this paper, an online remap strategy for memory repair, which ensures `fresh´ memory words are always used until the spare words run out, is proposed. The improvement of reliability for memory architectures and the area overhead introduced by the proposed scheme is evaluated.
Keywords
built-in self test; error correction codes; logic testing; memory architecture; ECC-based memory architecture; error correction codes; hard error correction; memory architectures; memory repair; online remap strategy; online self-repair capability; periodic online field test; reliability enhancement; soft error correction; synergistic approach; Built-in self-test; Circuit faults; Computer aided manufacturing; Error correction codes; Maintenance engineering; Reliability; System-on-chip; Built-in self-repair; ECC; Memory repair; online repair; reliability; remap CAM; remapping;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ETS), 2015 20th IEEE European
Conference_Location
Cluj-Napoca
Type
conf
DOI
10.1109/ETS.2015.7138734
Filename
7138734
Link To Document