Low-power CMOS voltage-Mode quaternary latched comparator

In this paper, a low-power CMOS voltage-mode quaternary latched comparator is presented. The proposed circuit operates in two modes. In comparison mode, it compares the input analog signal with three predefined threshold levels and returns a quaternary digit at the output accordingly, and in latch mode, it saves the output voltage which was generated in the previous mode. In addition to its operation as a quaternary latch in multiple-valued logic (MVL) circuits, the proposed comparator can also be used as a 4-level quantizer in such applications as quaternary data converters. The proposed circuit operates based on three parallel binary comparisons with different comparison characteristics. Designed in a 0.18-μm standard CMOS technology, the circuit exhibits simulation results which show power consumption of 20 μW from 1.8-V power supply while operating at 500 kHz. Also, in order to evaluate the functionality of the proposed quaternary latched comparator, a proof-of-concept functional prototype is built using off-the-shelf components.