Reconfigurable decoder for irregular random low density parity check matrix based on FPGA

Author

Musiyenko, Maksym ; Krainyk, Yaroslav ; Denysov, Oleksii

Author_Institution

Dept. of Inf. Technol. & Software Syst., Petro Mohyla Black Sea State Univ., Mykolaiv, Ukraine

fYear

2015

fDate

21-24 April 2015

Firstpage

498

Lastpage

503

Abstract

Method for design of partially parallel reconfigurable LDPC-decoder based on FPGA is presented in the paper. The decoder is able to process messages according to irregular random parity check matrix. The decoder can work with irregular random matrix and makes only small constraints on its structure. Parallel processing with several decoding units is considered. It is shown that decoder based on quad-port memory created on two-port memory can increase throughput in four times.

Keywords

field programmable gate arrays; multiport networks; parallel processing; parity check codes; FPGA; irregular random low density parity check matrix; irregular random parity check matrix; partially parallel reconfigurable LDPC decoder; quad port memory; reconfigurable decoder; two port memory; Decoding; Field programmable gate arrays; Finite element analysis; Indexes; Iterative decoding; Throughput; FPGA; LDPC; decoding unit; memory; parity check matrix; processing; throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics and Nanotechnology (ELNANO), 2015 IEEE 35th International Conference on

Conference_Location

Kiev

Type

conf

DOI

10.1109/ELNANO.2015.7146937

Filename

7146937