Low temperature multi-layer wafer level package for chip scale atomic clock (CSAC)

This paper demonstrates a five layers wafer level packaging. This technology has been specially developed for chip scale atomic clock system package. It includes a sealed vapor cell and two supports for vertical-cavity surface-emitting lasers and photodetector. The sealed cavity is achieved by Glass-Silicon-Glass (G-S-G) anodic bonding with high hermeticity, high reliability and low bonding temperature (400°C). The triple structure is supported by two silicon wafers. It is realized by photosensitive BCB adhesive bonding with good uniformity, relatively high mechanical strength (8Mpa) and low bonding temperature (250°C). The results show that over 60% of wafer is bonded with no void on the joint area and well aligned. At last, the stacked wafer is diced into individual chips.