Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug

Since integrating memory blocks on-chip becameaffordable, embedded logic analysis has been employed duringpost-silicon validation and debugging. Failing traces obtainedthrough embedded logic analysis can be used to understand functionaldesign errors, a problem that has been studied extensivelyover the past decade. In this paper, we show that post-processingfailing traces using a computational approach, based on Booleansatisfiability, can aid also the identification of electrically-induceddesign errors, e.g., bit-flips.