An Industrial Case Study: PaRent (Parallel & Concurrent) Testing for Complex Mixed-Signal Devices

Testing of every manufactured chip is an essential and crucial step in the semiconductor manufacturing process. It helps to ensure that customers get working chips that meet all the specifications. This is necessary to avoid the consequences and penalties that are incurred if a faulty chip is found by the customers. The current trend in the semiconductor industry is to attempt to increase the complexity of the chip while lowering its cost. This complicates the testing process because more testing is needed at a lower cost. Many solutions have been proposed, such as the use of cheaper testers and the use of embedded instruments for test and debug. Nevertheless, some tests and test requirements may not be amenable to these approaches. The multi-site test technique reduces the test cost by testing many units (i.e. physical chips) simultaneously. Concurrent testing is a related technique to reduce the test cost by testing many blocks within a single chip simultaneously. The PaRent approach, described in this paper, is a parallel (multi-site) and concurrent testing approach in which both techniques are used at the same time. This paper presents an industrial case study and describes the Design-for-Testability (DFT) requirements for successful PaRent testing of a high-volume mixed-signal System-on-Chip (SoC). Specifically, it describes the testing obstacles faced while testing a Power-Management Integrated Circuit (PMIC) that was not designed with concurrent testing in mind. Hardware and software optimizations for Automatic Test Equipment (ATE) to enhance the capabilities of PaRent testing are also described.