Run time write detection in SRAM

Author

Kumar, Satyendra ; Saha, Kaushik ; Gupta, Hariom

Author_Institution

Dept. of Electron. & Commun. Eng., Jaypee Inst. of Inf. Technol., Noida, India

fYear

2015

fDate

16-18 March 2015

Firstpage

328

Lastpage

333

Abstract

Data reliability of Static Random Access Memory (SRAM) cell is a major issue in deep submicron CMOS technology. In this paper, 8T SRAM cell has been proposed to implement a write failure detection scheme read after write. The cell has also been investigated with the conventional 6T SRAM cell for data stability, performance, write & read power, and area. The proposed cell demonstrates higher data stability specifically during read operation as the cell has high read SNM. The simulations have been carried out on 45nm technology node across the process voltage temperature (PVT) variations.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit modelling; integrated circuit noise; integrated circuit reliability; integrated circuit testing; PVT variations; SNM; SRAM cell; data reliability; data stability; deep submicron CMOS technology; process voltage temperature variations; run time write detection; size 45 nm; static noise margin; static random access memory; write failure detection scheme; Circuit stability; Inverters; Layout; SRAM cells; Simulation; Stability analysis; 6T SRAM; 8T SRAM; PVT; Read Access Time; Read Power; SNM; Write Access Time; Write Margin; Write Power;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing and Communication (ICSC), 2015 International Conference on

Conference_Location

Noida

Print_ISBN

978-1-4799-6760-5

Type

conf

DOI

10.1109/ICSPCom.2015.7150671

Filename

7150671