DocumentCode
719786
Title
Floating point FPGA architecture of PID controller
Author
Wadgaonkar, Jagannath ; Bhole, Kalyani ; Singh, Prateek
Author_Institution
Dept. of Instrum. & Control, Coll. of Eng. Pune, Pune, India
fYear
2015
fDate
28-30 May 2015
Firstpage
1259
Lastpage
1263
Abstract
Proportional Integral Derivative (PID) Controller is most well-known and consistent with industry. It is applied to many applications such as flow, temperature, motor control, robotic applications, biomedical applications, etc. Many applications demands fast response. Parallel implementation of proportional, integral, derivative action accelerates its response which can be achieved by using field programmable gate arrays (FPGA). Floating point implementation of PID gives more truthfulness. In this paper, a sincere effort has been made to design and implement the floating point parallel architecture of PID controller using SPARTAN 3E(XC3S-500e) FPGA.
Keywords
control engineering computing; field programmable gate arrays; parallel architectures; three-term control; PID controller; SPARTAN 3E FPGA; field programmable gate array; floating point FPGA architecture; floating point parallel architecture; proportional integral derivative controller; Computer architecture; Field programmable gate arrays; Hardware; Industries; Logic gates; MATLAB; Mathematical model; FPGA; HDL verilog; IEEE 754; Matlab; system generator;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Instrumentation and Control (ICIC), 2015 International Conference on
Conference_Location
Pune
Type
conf
DOI
10.1109/IIC.2015.7150941
Filename
7150941
Link To Document