DocumentCode
720602
Title
Analyzing Isochronic Forks with Potential Causality
Author
Manohar, Rajit ; Moses, Yoram
Author_Institution
Cornell NYC Tech, New York, NY, USA
fYear
2015
fDate
4-6 May 2015
Firstpage
69
Lastpage
76
Abstract
Asynchrony and concurrency are fundamental notions in the fields of asynchronous circuits as well as distributed systems. This paper treats asynchronous circuits as a special class of distributed systems. We adapt the distributed systems notion of potential causality to asynchronous circuits, and use it to provide a formal proof of the precise nature of the isochronic fork timing assumption in quasi delay-insensitive (QDI) circuits. Our proofs provide a transparent analysis that provides better intuition regarding the operation of QDI circuits. We build on our theory to rigorously establish several "folk theorems" about identifying isochronic forks in QDI circuits.
Keywords
asynchronous circuits; causality; logic design; network analysis; synchronisation; QDI circuits; asynchronous circuits; distributed systems; isochronic fork timing assumption; quasidelay-insensitive circuits; Asynchronous circuits; Delays; Integrated circuit modeling; Logic gates; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Asynchronous Circuits and Systems (ASYNC), 2015 21st IEEE International Symposium on
Conference_Location
Mountain View, CA
ISSN
1522-8681
Type
conf
DOI
10.1109/ASYNC.2015.19
Filename
7152693
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