Variation-aware energy-delay optimization method for device/circuit co-design

Author

Junyao Wang ; Xiaobo Jiang ; Xingsheng Wang ; Runsheng Wang ; Binjie Cheng ; Asenov, Asen ; Lan Wei ; Ru Huang

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing, China

fYear

2015

fDate

15-16 March 2015

Firstpage

1

Lastpage

3

Abstract

A new variation-aware energy-delay optimization method is proposed for device-circuit co-design in nanoscale CMOS digital circuits design. Yield is added into traditional energy-delay (ED) optimization method as a figure of merit to take account of ED variation caused by major process variation sources in nanoscale technology. Threshold voltage and supply voltage can be co-optimized to meet any customized energy-delay-yield (EDY) requirements. The efficiency and accuracy of the proposed EDY method is confirmed by circuit simulations targeting at different digital circuit applications. Results from optimization and simulation show great advantage in avoiding over-design compared with the conventional ED method. Furthermore, the extendibility of the proposed method to include reliability-induced degradation and variation is exhibited.

Keywords

CMOS digital integrated circuits; integrated circuit design; integrated circuit reliability; integrated circuit yield; nanoelectronics; ED variation; EDY method; circuit simulation; complementary metal oxide semiconductor; device-circuit codesign; energy-delay-yield; nanoscale CMOS digital circuit design; nanoscale technology; reliability-induced degradation; supply voltage; threshold voltage; variation-aware energy-delay optimization method; CMOS integrated circuits; CMOS technology; Delays; FinFETs; Nanoscale devices; Reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Technology International Conference (CSTIC), 2015 China

Conference_Location

Shanghai

ISSN

2158-2297

Type

conf

DOI

10.1109/CSTIC.2015.7153331

Filename

7153331