High voltage NLDMOS with multiple-RESURF structure to achieve improved on-resistance

Author

Shao-Ming Yang ; Hema, Ep ; Mrinal, Aryadeep ; Amanullah, Md ; Gene Sheu ; Pa Chen

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Asia Univ., Taichung, Taiwan

fYear

2015

fDate

15-16 March 2015

Firstpage

1

Lastpage

3

Abstract

In this paper, we present high voltage NLDMOS structure with multiple RSEURF concepts. The NLDMOS is based on 0.35μm BCD process. The multiple RESURF device base on charge balance theory using P-top and N-top to achieve high breakdown voltage and low on-resistance. The 2D simulation result compares the conventional single RESURF NLDMOS structure and the new structure with multiple RESURF devices. The new device concept help to improve the on-resistance up to 20% were as keeping the breakdown voltage still in the acceptable range for 40V rated device. The 2D simulation is using by process simulator Tsuprem4 and Medici to verify the device concept and identify the electrical characteristics.

Keywords

MOS integrated circuits; electric breakdown; 2D simulation result; charge balance theory; high breakdown voltage; high voltage NLDMOS; low on-resistance; multiple-RESURF structure; size 0.35 mum; voltage 40 V; Electric fields; Implants; Logic gates; Periodic structures; Silicon; Simulation; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Technology International Conference (CSTIC), 2015 China

Conference_Location

Shanghai

ISSN

2158-2297

Type

conf

DOI

10.1109/CSTIC.2015.7153334

Filename

7153334