The problems and solutions in 40 nm node dual gate lithography process development

When the semiconductor technology steps into 40 nm node and beyond, the defect becomes increasingly difficult to be detected and removed. In this paper, we studied one kind of bump like defect which was first suspected to originate from 40 nm dual gate lithography process. The Bump defect appearing after dual gate photoresist wet striping has a great impact on thin gate oxidation and is a major yield killer. Our analysis showed that the defect is caused by OH^- generated during thick gate oxide process which will affect the light acid reaction occurring in lithography coating process or the photoresist striping residual in the wet photoresist striping process. Based on the above analysis, we have optimized our coating process to reduce the defect and finally the yield of our devices is recovered.