A new staircase test method for copper via electromigration on CMOS wafers

A highly accelerated test method was developed that can stress copper vias on a wafer to 100% failure in just a few minutes. Other test methods like constant current, constant voltage and isothermal tests can take many hours to reach even 50% failure. Most of these test methods require packaging, special test boards and ovens. Unlike constant stress methods our method uses a current “staircase” ramp to apply increasing stress to the vias until they fail. The high current causes self-heating which accelerates the stress. The temperature during stress is monitored by continuously measuring the via resistance using a 4-terminal Kelvin method. The maximum stress temperature is about 350 °C for 1-second stress steps. Even at this high temperature, our test results agree reasonably well with Black´s equation with activation energy Ea = 0.9 eV and current exponent n = 1. Preliminary test results predict that the MTTF of our Via-4 samples will be much greater than 10 years at room temperature.