Accelerating timing closure using incremental advanced OCV

As technology scales into the deep submicron regime, on chip variation (OCV) has become a dominant factor which influences the performance and yield of the circuits. Considering OCV analysis in static timing analysis (STA) tools is therefore one of the most crucial issues in LSI designs nowadays. Advanced OCV (AOCV) is a widely deployed technique in industry to account for OCV effects at smaller geometries. However, it is also known to suffer from the runtime overhead problem for incremental timing update. In this paper, we propose the first incremental AOCV methodology in the literature, which makes AOCV suitable for use in the inner loop of physical synthesis or other optimization tools. This approach has been implemented in an industrial place-and-route tool and experimental results on industrial designs show that using AOCV together with the industrial optimization flow can significantly reduce the pessimism and improve the final QoR compared to the traditional OCV based flow.