Initialization for time delay digital tanlock loop

This paper presents an improved second-order time delay digital tanlock loop (TDTL) system. It uses an initialization technique to enhance some of the main performance parameters of the original TDTL loop and hence overcome some of the inherent loop limitations. A one-bit Sigma-Delta modulator is used to initialize the DCO (digital controlled oscillator) for coarse tuning mode in order to enhance the noise immunity of the TDTL loop. An evaluation of the improved architecture using Simulink/Matlab, under noise-free as well as noisy conditions, demonstrated marked improvements in performance compared to the original TDTL.