DocumentCode
722746
Title
Comparative study regarding two implementations of an SEC-DED code with FPGA circuits
Author
Novac, O. ; Sztrik, J. ; Grava, C.
Author_Institution
Comput. & Inf. Technol. Dept., Univ. of Oradea, Oradea, Romania
fYear
2015
fDate
11-12 June 2015
Firstpage
1
Lastpage
4
Abstract
In this paper we compare two different implementation of an SEC-DED HSIAO code. This comparison is made to select which is the best method to achieve better memory, from reliability point of view. In this paper HSIAO code is used, because is efficient for single errors correction and double error detection that appear in cache memory hierarchy. Also, we have implemented the HSIAO code with FPGA Xilinx circuits for both implementations.
Keywords
cache storage; error correction codes; error detection; field programmable gate arrays; FPGA circuits; HSIAO code; SEC-DED code; cache memory hierarchy; double error detection; single errors correction; Cache memory; Computers; Error correction codes; Europe; Field programmable gate arrays; Mathematical model; Reliability; FPGA circuits; HSIAO code; SEC-DED code; cache;
fLanguage
English
Publisher
ieee
Conference_Titel
Engineering of Modern Electric Systems (EMES), 2015 13th International Conference on
Conference_Location
Oradea
Print_ISBN
978-1-4799-7649-2
Type
conf
DOI
10.1109/EMES.2015.7158432
Filename
7158432
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