III–V/Ge MOSFETs and tunneling FETs on Si platform for low power logic applications

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for low power advanced LSIs in the future, because of the expectation of high current drive. In addition, Tunneling-FET (TFET) using III-V/Ge-based materials can also be one of the important device families with steep slope device switching, which is mandatory for the ultra-low power devices. In this paper, we address the device engineering of III-V/Ge channel formation, low resistivity source/drain (S/D) with steep profile and MOS gate stacks for realizing these devices, compatible with the Si platform.