A Low Power Logic-Compatible Multi-Bit Memory Bit Cell Architecture With Differential Pair and Current Stop Constructs

The architecture in this work uses a logic-compatible CMOS process particularly suitable for embedded applications. The differential pair construct causes the read and refresh power to be independent of any process parameter including the within-die threshold voltage. The current stop feature keeps the read voltage transition low to further minimize read power. The bit cell operates in both single bit BASE2 and multi-bit BASE4 modes. An expression for the read signal was verified with bit cell simulations. These simulations also compare the performance impact of threshold voltage variance in this architecture with a standard gain cell. A DRAM bit cell array was fabricated in the XFab 180 nm CMOS process. Measured waveforms closely match theoretical results obtained from a system simulation. The silicon retention time was measured at room temperature and is greater than 150 ms in BASE2 mode and greater than 75 ms in BASE4 mode. 180 nm, 25C analysis predicts 0.8 uW/Mbit refresh power at 630 MHz, the lowest in the literature. Further: the memory bit cell architecture presented here has a refresh power delay product several times lower than any other published architecture.