Thermal stress destruction analysis in low-k layer by via-last TSV structure

Investigation of the thermo-mechanical stress by using finite element analysis (FEA) and the destruction verification with thermal cycle (TC) test were carried out. It was found that the back end of line (BEOL) dielectric layer near the through silicon via (TSV) was cracked in case of a RT-400 °C heat cycle. Thermo-mechanical stress concentration at the TSV landing area has been confirmed by the results of FEA simulation. Dielectric layer cracking was caused at interface between the dielectric layer and edge corner of the land metal (M1) contact pad connected with the TSV. And the slit voids at the TSV sidewall were observed on the area of insufficient of side coverage of the titanium (Ti) metal barrier liner at the TSV bottom. The BEOL deformation of the metal contact area was also clear that the low-k cracks tend to occur at non constraint condition of the TSV sidewall as the slit void. In this paper shows that the interface becomes free surface as non-constrained condition caused by poor liner coverage, and it was insufficient interface adhesion to suppress the thermal expansion deformation of copper. This study provides that low-k layer cracking can be avoided by adopting optimized stress dispersion design to the BEOL low-k/copper with TSV landing pad structure.