Design for reliability with a new modeling methodology for Chip to Package Interaction

Chip to Package Interaction (CPI) is becoming a critical reliability issue due to the adoption of new materials used for Si backend interconnects like extreme low k (ELK) dielectric, Pb free solder and Cu pillar bumping and the advanced packaging technologies such as high performance flip chip BGA and 2.5D/3D packages. CPI failures are primarily inside the Si die with the typical failure modes such as ELK fracture; crack initiation and propagation at the Cu/ELK interface and the bump interconnect fracture, etc.CPI stress involves Si design, fabrication, package design, assembly, material selection and even the end use usage conditions. How to design CPI reliability in early Si design remains a challenging issue because there is no common platform for all people involved to work on the same issue. Currently, the Integrated Circuit (IC) designers, foundry and Outsource Assembly and Test (OSAT) are dealing with the same issue separately and normally don´t talk to each other. The fabless Integrated Circuit (IC) design house can only rely on the foundry design rules and OSAT´s CPI data to assess the reliability. However, both OSAT and foundry can only treat the Si either as a piece of solid material or with simplified interconnect structures; it does not represent the actual metal stack-up in a Si product and may not be able to uncover all possible CPI failures. With the same interaction stress from the package, pad structures have a great effect on the CPI failures; for example, pads with active circuits underneath are more vulnerable to CPI failures. These Si design and layout related CPI issues need to be addressed early in the Si design phase. Otherwise, it would be too late and very costly to fix these issues when the CPI failures are uncovered during assembly or reliability tests. This paper proposed a methodology of designing for Chip to Package Interaction (CPI) reliability. That provides a common platform to make it possible for every party to interact to eac- other so the CPI reliability can be designed in at early chip design phases.