Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA

The Wave Dynamic Differential Logic (WDDL) offers an effective way to resist Side Channel Attacks (SCA). But, it suffers from early propagation and routing imbalance between dual signals. In this paper, we deal first with the EPE problem. We study the security of BCDL logic, which is known to counter early propagation, and we compare it to WDDL logic. We target a custom tree-based FPGA of 2048 cells. Next, we try to solve the routing imbalance problem by performing an adjacent placement and a timing balance driven routing. Side channel analyses are performed on FPGA circuit implementing PRESENT crypto-processor. Experimental results show that both avoiding early propagation and diminishing routing imbalance by controlling placement and routing tools enhance the design security against SCA.